features applications photodiode photodiode array with amplifier photodiode array combined with signal processing circuit chip s8865-256, S8865-256G s8865-256 and S8865-256G are si photodiode arrays combined with a signal processing circuit chip. the signal processing circuit chip is formed by cmos process and incorporates a timing generator, shift register, charge amplifier array, clamp circuit and hold circuit, ma king the external circuit configuration simple. a long, narrow image sensor can also be configured by arranging multiple arrays in a row. for x-r ay detection applications, types with fluorescent paper affixed on the active area are also available. l element pitch: 0.2 mm pitch 256 ch l 5 v power supply operation l simultaneous integration by using a charge amplifier array l sequential readout with a shift register (data rate: 1 mhz max.) l low dark current due to zero-bias photodiode operation l integrated clamp circuit allows low noise and wide dynamic range l integrated timing generator allows operation at two different input pulse timings (reset, clock) l types with phosphor screen affixed on the active area are available for x-ray detection: S8865-256G l long line sensors l line sensors for x-ray detection specifications of active area parameter symbol * 1 value unit element pitch p 0.2 mm element width w 0.1 mm element height h 0.3 mm number of elements - 256 - active area length - 51.2 mm *1: refer to following figure. h w p photodiode enlarged view of active area kmpdc0072eb 1
photodiode array with amplifier s8865-256, S8865-256G absolute maximum ratings parameter symbol rated value unit supply voltage vdd -0.3 to +6 v reference voltage vref -0.3 to +6 v photodiode voltage vpd -0.3 to +6 v gain selection terminal voltage vgain -0.3 to +6 v master/slave selection voltage vms -0.3 to +6 v clock pulse voltage v ( clk) -0.3 to +6 v reset pulse voltage v ( reset) -0.3 to +6 v external start pulse voltage v ( extst) -0.3 to +6 v operating temperature * 2 topr -5 to +60 c storage temperature ts t g -10 to +70 c *2: no condensation recommended terminal voltage parameter symbol min. typ. max. unit supply voltage vdd 4.75 5 5.25 v reference voltage vref 4 4.5 4.75 v photodiode voltage vpd - vref - v high gain vdd-0.25 vdd vdd+0.25 v gain selection terminal voltage low gain vgain 0 - 0.4 v high level * 3 vdd-0.25 vdd vdd+0.25 v master/slave selection voltage low level * 4 vms 0-0.4v high level vdd-0.25 vdd vdd+0.25 v clock pulse voltage low level v (clk) 0 - 0.4 v high level vdd-0.25 vdd vdd+0.25 v reset pulse voltage low level v (reset) 0-0.4v high level vdd-0.25 vdd vdd+0.25 v external start pulse voltage low level v (exesp) 0 - 0.4 v *3: parallel *4: serial at 2nd or later stages electrical characteristics [ ta=25 c, vdd=5 v, v (clk)=v (reset)=5 v] parameter symbol min. typ. max. unit clock pulse frequency * 5 f (clk) 40 - 4000 khz output impedance zo - 3 - k ? power consumption p - 360 - mw high gain - 0.5 - charge amp feedback capacitance low gain cf - 1 - pf *5: video data rate is 1/4 of clock pulse frequency f (clk). 2
photodiode array with amplifier s8865-256, S8865-256G electrical/optical characteristics [ta=25 c, vdd=5 v, v (clk)=v (reset)=5 v, vgain=5 v (high gain), 0 v (low gain)] parameter symbol min. typ. max. unit spectral response range 200 to 1000 nm peak sensitivity wavelength p - 720 - nm high gain - 0.002 0.02 dark output voltage * 6 low gain vd - 0.001 0.01 mv saturation output voltage vsat 3 3.5 - v high gain - 15 - saturation exposure * 7 low gain esat -30- m lx s high gain - 250 - photo sensitivity low gain s - 125 - v/ lx s photo response non-uniformity * 8 prnu - - 10 % high gain - 0.6 - noise * 9 low gain n - 0.3 - mvrms output offset voltage * 10 vos - vref - v *6: integration time ts=1 ms *7: measured with a 2856 k tungsten lamp *8: when the photodiode array is exposed to uniform light which is 50 % of the saturation exposure, the photo response non- uniformity (prnu) is defined as follows: prnu = ? x/x 100 (%) where x is the average output of all elements and ? x is the difference between the maximum and minimum outputs. *9: measured with a video data rate of 50 khz and ts=1 ms in dark state *10: video output is negative-going output with respect to the output offset voltage. output offset voltage vref=4.5 v typ. saturation state dark state saturation output voltage vsat=3.5 v typ. 1 v typ. gnd 0.5 0.4 0.3 0.2 0.1 0 200 400 600 800 wavelength (nm) 1000 1200 photo sensitivity (a/w) (ta=25 ?c) 1 4 reset extsp vms vdd gnd clk vref vgain vpd 2 10 11 12 5 6 7 timing generator shift register hold circuit charge amp array photodiode array 3trig 8 eos 9 video 12345 n-1n kmpdc0152ea kmpdb0220ea kmpdc0153ea spectral response (measurement example) block diagram output waveform of one element 3
photodiode array with amplifier s8865-256, S8865-256G 1 2 3 1 2 3 4 5 14 15 16 17 video output period clk reset video trig eos tf (clk) tf (reset) tpw (clk1) t1 t2 tpw (clk2) tpw (reset1) tpw (reset2) tr (clk) tpw (reset2) 18 19 20 1 2 n-1 n tr (reset) tpw (reset1) kmpdc0154ec timing chart parameter symbol min. typ. max. unit clock pulse width tpw (clk1), tpw (clk2) 125 - 12500 ns clock pulse rise/fall times tr (clk), tf (clk) 0 20 30 ns reset pulse width 1 tpw (reset1) 10 - - s reset pulse width 2 tpw (reset2) 20 - - s reset pulse rise/fall times tr (reset), tf (reset) 0 20 30 ns clock pulse-reset pulse timing 1 t1 -20 0 20 ns clock pulse-reset pulse timing 2 t2 -20 0 20 ns 1. the internal timing circuit starts operation at a fall of clk immediately after a reset pulse sets to low. 2. when a fall of clk is counted as "1 clock", the video signal at the 1st channel appears between "18.5 clocks and 20 clocks". then a video signal appears every 4 clocks. 3. signal charge integration time equals the high period of a reset pulse. however, the charge integration does not start at the rise of a reset pulse but starts at the 8th clock after the rise of the reset pulse and ends at the 8th clock after the fall of the reset pulse. signals integrated within this period are sequentially read out as time-series signals by the shift register operation when the reset pulse next changes from high to low. the rise and fall of a reset pulse must be synchronized with the fall of a clk pulse, but the rise of a reset pulse must be set outside the video output period. one cycle of reset pulses cannot be set shorter than the time equal to "(video signal readout period 16.5 + 4) n (number of pixels)" clocks. 4
photodiode array with amplifier s8865-256, S8865-256G 51.2 -0 +0.2 34.02 2 1 26 ( 4) 2.2 (26 ) 0.64 0.64 25 p2.54 12 = 30.48 10.0 2.54 8.0 * 11 40.0 0.15 6.9 6.0 6.6 40.0 cmos1 cmos2 1.6 17.0 3.0 2.54 2.28 direction of scan photodiode 1 ch phosphor screen * 12 kmpda0191ea dimensional outline (unit: mm) *11: distance from the bottom of the board to the center of active area board: g10 glass epoxy connector: jae (japan aviation electronics industry, limited) ps-26pe-d4lt1-pn1 *12:photodiode array with phosphor screen: S8865-256G only material gd 2 o 2 s: tb phosphor thickness 300 m typ. detectable energy range 30k to 100 kev 5 pin connection pin no. cmos1 pin no. cmos2 name note 1 vpd 14 vpd photodiode voltage voltage input 2 reset 15 reset reset pulse pulse input 3 clk 16 clk clock pulse pulse input 4 trig 17 trig trigger pulse positive-going pulse output 5 extsp 18 extsp external start pulse pulse input 6 vms 19 vms master/slave selection supply voltage voltage input 7 vdd 20 vdd supply voltage voltage input 8 gnd 21 gnd ground 9 eos 22 eos end of scan negative-going pulse output 10 video 23 video video output negative-going output with respect to vref 11 vref 24 vref reference voltage voltage input 12 vg 25 vg gain-selection terminal voltage voltage input 13 vpd 26 vpd photodiode voltage voltage input
hamamatsu photonics k.k., solid state division 1126-1 ichino-cho, higashi-ku, hamamatsu city, 435-8558 japan, telephone: (81) 53-434-3311, fax: (81) 53-434-5184, www.hamamatsu.com u.s.a.: hamamatsu corporation: 360 foothill road, p.o.box 6910, bridgewater, n.j. 08807-0910, u.s.a., telephone: (1) 908-231-0 960, fax: (1) 908-231-1218 germany: hamamatsu photonics deutschland gmbh: arzbergerstr. 10, d-82211 herrsching am ammersee, germany, telephone: (49) 08152 -3750, fax: (49) 08152-2658 france: hamamatsu photonics france s.a.r.l.: 19, rue du saule trapu, parc du moulin de massy, 91882 massy cedex, france, teleph one: 33-(1) 69 53 71 00, fax: 33-(1) 69 53 71 10 united kingdom: hamamatsu photonics uk limited: 2 howard court, 10 tewin road, welwyn garden city, hertfordshire al7 1bw, unit ed kingdom, telephone: (44) 1707-294888, fax: (44) 1707-325777 north europe: hamamatsu photonics norden ab: smidesv ? gen 12, se-171 41 solna, sweden, telephone: (46) 8-509-031-00, fax: (46) 8-509-031-01 italy: hamamatsu photonics italia s.r.l.: strada della moia, 1/e, 20020 arese, (milano), italy, telephone: (39) 02-935-81-733, fax: (39) 02-935-81-741 information furnished by hamamatsu is believed to be reliable. however, no responsibility is assumed for possible inaccuracies or omissions. specifications are subject to change without notice. no patent rights are granted to any of the circuits described herein. ?200 6 hamamatsu photonics k.k. cat. no. kmpd1087e01 jul. 2006 dn photodiode array with amplifier s8865-256, S8865-256G type vms extsp avdd vdd b gnd preceding sensor eos should be input gain selection terminal voltage setting vdd: high gain (cf: 0.5 pf) gnd: low gain (cf: 1 pf) readout methods and settings signals of channels 1 through 126 are output from cmos1, while signals of channels 129 through 256 are output from cmos2. the following two readout methods are available. (1) serial readout method cmos1 and cmos2 are connected in serial and the signals of channels 1 through 256 are sequentially read out from one output line. set cmos1 as in a in the table below, and set cmos2 as in b . cmos1 and cmos2 should be connected to the same clk and reset lines, and their video output terminals to one line. (2) parallel readout method 128 channel signals are output in parallel respectively from the output lines of cmos1 and cmos2. set both cmos1 and cmos2 as in ? a ? in the table below. readout circuit check that pulse signals meet the required pulse conditions before supplying them to the input terminals. video output should be amplified by an operational amplifier that is connected close to the sensor. cautions during use (1) the signal processing circuit chips of s8865 series are protected against static electricity. however, in order to prevent possible damage to the chip, implement electrostatic countermeasures such as grounding of the operator, work table and tools. furthermore, the devices must be protected against surge voltages from external equipment. (2) since the photodiode array chip is not protected, handle it carefully so it will not become contaminated or scratched. photodiode array performance may deteriorate if operated at high temperatures and humidity, so the housing should be designed to be airtight. the signal processing circuit chip and its wire bonding are covered with a resin coating for protection, but never touch these portions. in addition, take care when installing the board so that it does not warp. (3) S8865-256G signal processing ic chip performance will drop if subjected to x-rays. protect the ic chip from x-rays by installing a lead shield. 6 connection example serial readout method parallel readout method vpd 1 reset (1) 2 clk (1) reset clk 3 trig (1) 4 extsp (1) 5 vms (1) 6 vdd 7 gnd vdd gnd 8 eos (1) 9 video (1) 10 vref 11 vgain vref vgain 12 vpd 13 vpd 14 reset (2) tr i g or logic ic 74hc32 15 clk (2) 16 trig (2) 17 extsp (2) 18 vms (2) 19 vdd 20 gnd 21 eos (2) 22 video (2) eos video 23 vref 24 vgain 25 vpd 26 cmos2 cmos1 kmpdc0222ea reset (1) 1 clk (1) 2 trig (1) reset clk 3 extsp (1) 4 vms (1) 5 vdd 6 gnd 7 eos (1) vdd gnd 8 video (1) 9 vref 10 vgain 11 vpd vref vgain 12 reset (2) 1 clk (2) 2 trig (2) 3 extsp (2) 4 vms (2) 5 vdd 6 gnd 7 eos (2) 8 video (2) 9 vref 10 vgain 11 vpd 12 trig2 trig1 eos2 video2 eos1 video1 cmos2 cmos1 kmpdc0223ea
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